Extended BDD's: trading off canonicity for structure in verification algorithms
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors present an extension to binary decision diagrams (BDDs) that exploits the information contained in the structure of the circuit to produce a compact, semicanonical representation. The extended BDDs (XBDDs) retain many of the advantages of BDDs while at the same time allowing one to deal with larger circuits. Using XBDDs, it is possible to verify circuits for which the BDDs could not be built in the same amount of space. Results of the application of XBDDs to combinational multipliers are presented.<>Keywords
This publication has 10 references indexed in Scilit:
- New ATPG techniques for logic optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Logic verification using binary decision diagrams in a logic synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Performance enhancements in BOLD using 'implications'Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Variable ordering and selection of FSM traversalPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- ATPG aspects of FSM verificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient implementation of a BDD packagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Verification algorithms for VLSI synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- Representation of Switching Circuits by Binary-Decision ProgramsBell System Technical Journal, 1959