A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance used for input matching
- 3 April 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Microwave and Wireless Components Letters
- Vol. 16 (4) , 188-190
- https://doi.org/10.1109/lmwc.2006.872128
Abstract
Design and measured results of a fully integrated 5.7-GHz CMOS low-noise amplifier (LNA) is presented. To design this LNA, the parasitic input resistance of a metal-oxide-semiconductor field-effect transistor (MOSFET) is converted to 50/spl Omega/ by a simple L-C network, hence eliminating the need for source degeneration. It is shown, by means of compact expressions, that this matching method enhances the effective transconductance of the LNA by a factor that is inversely proportional to a MOSFET's input resistance. The effect of our proposed method on the noise figure (NF) of the LNA is also discussed. With an 11.45-dB power gain and a 3.4-dB NF at 4mW of dc power, the presented LNA achieves the best overall performance when compared with the most recently published LNAs.Keywords
This publication has 7 references indexed in Scilit:
- MOSFET Modeling for RF IC DesignIEEE Transactions on Electron Devices, 2005
- A 2.17-dB NF 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumptionIEEE Transactions on Microwave Theory and Techniques, 2005
- Analytical Modeling of MOSFETs Channel Noise and Noise ParametersIEEE Transactions on Electron Devices, 2004
- 26–42 GHz SOI CMOS Low Noise AmplifierIEEE Journal of Solid-State Circuits, 2004
- A 5.7-GHz 0.18-μm CMOS gain-controlled differential LNA with current reuse for WLAN receiverIEEE Microwave and Wireless Components Letters, 2003
- A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistanceIEEE Journal of Solid-State Circuits, 2003
- A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002