The constrained via minimization problem for PCB and VLSI design

Publisher Website

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/dac.1988.14818

Abstract

No abstract available

Keywords

This publication has 6 references indexed in Scilit:

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A graph-theoretic via minimization algorithm for two-layer printed circuit boards
IEEE Transactions on Circuits and Systems, 1983
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An Optimum Layer Assignment for Routing in ICs and PCBs
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981
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SIAM Journal on Computing, 1977
Maximum matching and a polyhedron with 0,1-vertices
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