Hysteresis in neural-type circuits
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 993-996 vol.2
- https://doi.org/10.1109/iscas.1988.15091
Abstract
The mechanism of generation of hysteresis in a neural-type cell is presented. To make the theory tractable, it is assumed that the hysteresis determining MOS transistors operate in their square-law region when turned on. A set of equations is obtained that can be used for the design of MOS transistor neural-type cells which give pulse code modulation for the coding of information in neural-type systems.<>Keywords
This publication has 1 reference indexed in Scilit:
- An integrable MOS neuristor lineProceedings of the IEEE, 1976