Toroidal Neural Network: Architecture and Processor Granularity Issues

This publication has 7 references indexed in Scilit:

• A scaleable waferscale architecture for real-time 3-D image generation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Delay-insensitive codes — an overview
  Distributed Computing, 1988
• Parallel architectures for artificial neural nets
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1988
• Neural network simulation at Warp speed: how we got 17 million connections per second
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1988
• Learning Internal Representations by Error Propagation
  Published by Defense Technical Information Center (DTIC) ,1985
• Wafer-scale integration-a fault-tolerant procedure
  IEEE Journal of Solid-State Circuits, 1978
• Anomalous Behavior of Synchronizer and Arbiter Circuits
  IEEE Transactions on Computers, 1973