An alternative architecture for on-chip global interconnect: segmented bus power modeling
- 27 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 1062-1065
- https://doi.org/10.1109/acssc.1998.751425
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
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