An evaluation of parallel simulated annealing strategies with application to standard cell placement
- 1 April 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 16 (4) , 398-410
- https://doi.org/10.1109/43.602476
Abstract
No abstract availableThis publication has 29 references indexed in Scilit:
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