A portable parallel algorithm for logic synthesis using transduction
- 1 May 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 13 (5) , 566-580
- https://doi.org/10.1109/43.277630
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- A Shared Memory Parallel Algorithm for Logic SynthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Logic Partitioning and Resynthesis for TestabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Multi-level logic optimization using binary decision diagramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- ProperCAD: a portable object-oriented parallel environment for VLSI CADPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- ProperSYN: A portable parallel algorithm for logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A parallel PLA minimization programPublished by Association for Computing Machinery (ACM) ,1987
- Logic verification algorithms and their parallel implementationPublished by Association for Computing Machinery (ACM) ,1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- A Rule-Based System for Optimizing Combinational LogicIEEE Design & Test of Computers, 1985