CMOS-SRAM soft-error simulation system
- 1 January 1994
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 32, 339-343
- https://doi.org/10.1109/relphy.1994.307815
Abstract
A soft-error simulation system for designing CMOS-SRAM cells is presented. We propose a new noise current model and combine it with the SRAM's equivalent circuit. Simulation results agree with those from a compulsory exposure experiment. Our system predicts the field soft-error rate from the alpha-particle emission rate, mask layout, and process conditions.<>Keywords
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