Faster SAT and smaller BDDs via common function structure

This publication has 16 references indexed in Scilit:

• Multilevel Hypergraph Partitioning: Application In Vlsi Domain
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Combinational profiles of sequential benchmark circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Logic verification using binary decision diagrams in a logic synthesis environment
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A comparative study of two Boolean formulations of FPGA detailed routing constraints
  Published by Association for Computing Machinery (ACM) ,2001
• Can recursive bisection alone produce routable placements?
  Published by Association for Computing Machinery (ACM) ,2000
• Relaxation and clustering in a local search framework
  Published by Association for Computing Machinery (ACM) ,1999
• FPGA routing and routability estimation via Boolean satisfiability
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998
• Combinational test generation using satisfiability
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
• Test pattern generation using Boolean satisfiability
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
• Graph-Based Algorithms for Boolean Function Manipulation
  IEEE Transactions on Computers, 1986