Modeling Rapid Annealing in Digital Integrated Circuits
- 1 January 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 26 (6) , 4750-4757
- https://doi.org/10.1109/tns.1979.4330222
Abstract
An analytical model for the effects of rapid annealing in narrow base bipolar transistors has been developed. This model utilizes transistor base-emitter voltage and an empirical curve to calculate annealing factor with time. The model has been incorporated into the TRAC circuit analysis code and used to predict the time-dependent response of a low-power Schottky TTL NAND gate and a four-bit shift register as a function of neutron fluence and operating condition.Keywords
This publication has 11 references indexed in Scilit:
- Radiation effects on semiconductor devicesProceedings of the IEEE, 1974
- Short-Term Annealing in Transistors Irradiated in the Biased-Off ModeIEEE Transactions on Nuclear Science, 1971
- Designing Ultrahard Bipolar TransistorsIEEE Transactions on Nuclear Science, 1971
- Application of Neutron Damage Models to Semiconductor Device StudiesIEEE Transactions on Nuclear Science, 1970
- Nuclear Radiation Enhancement of Transistor Forward Gain at High FrequenciesIEEE Transactions on Nuclear Science, 1970
- PHOTOCONDUCTIVITY STUDY OF DIVACANCY FORMATION IN NEUTRON-IRRADIATED SiApplied Physics Letters, 1969
- Transistor Schottky-barrier-diode integrated logic circuitIEEE Journal of Solid-State Circuits, 1969
- Thermal and Injection Annealing of Neutron-Irradiated p-Type Silicon between 76°K and 300°KIEEE Transactions on Nuclear Science, 1969
- Injection Dependence of Transient Annealing in Neutron-Irradiated Silicon DevicesIEEE Transactions on Nuclear Science, 1967
- Transient Annealing in Sekiconductor Devices Following Pulsed Neutron IrradiationIEEE Transactions on Nuclear Science, 1966