Differential pass-transistor logic

1 July 1993

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Circuits and Devices Magazine

Vol. 9 (4) , 23-28
https://doi.org/10.1109/101.250230

Abstract

Differential pass-transistor logic (DPTL), which offers the noise immunity needed to use the unique switching properties of FETs in realizing switching network efficiencies, is discussed. CMOS DPTL offers significant power-delay product advantages over conventional CMOS logic for both 5-V and 3-V power supplies. These features are achieved by DPTL's fewer and smaller parasitic capacitances, which are the result of significantly lower device counts combined with emphasized usage of minimum-size, n-channel pass-transistors. Substantial benefits are also obtained by using DPTL with depletion and enhancement/depletion GaAs MESFET technologies. Experiments show that GaAs DPTL offers substantial power-delay-product reductions over conventional GaAs realizations. Compared to CMOS DPTL, GaAs DPTL consumes less power at very high frequencies, a consequence of the electronic properties of GaAs and the smaller signal swings used in emitter/drain (E/D) DPTL.

Keywords

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