Erasure and Error Decoding for Semiconductor Memories
- 1 August 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-27 (8) , 696-705
- https://doi.org/10.1109/tc.1978.1675176
Abstract
In this paper we introduce and evaluate error correction methods which takes into account the special properties of failure modes in semiconductor memories. We assume that the memory faults are of the type stuck-to 1 or 0. Thus the fault, once it has occurred, is located to a specific position in a memory word. The position may be found and this fact makes it convenient to use erasure correction, rather than random error correction.Keywords
This publication has 13 references indexed in Scilit:
- Asymptotically optimal soft decision decoding algorithms for Hamming codesElectronics Letters, 1977
- Errors-and-erasures decoding of binary majority-logic-decodable codesElectronics Letters, 1976
- Implementation of an Experimental Fault-Tolerant Memory SystemIEEE Transactions on Computers, 1976
- Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability EnhancementIEEE Transactions on Computers, 1975
- One-step majority-logic decoding with symbol reliability information (Corresp.)IEEE Transactions on Information Theory, 1975
- Lookaside Techniques for Minimum Circuit Memory TranslatorsIEEE Transactions on Computers, 1973
- b-Adjacent Error CorrectionIBM Journal of Research and Development, 1970
- A Class of Optimal Minimum Odd-weight-column SEC-DED CodesIBM Journal of Research and Development, 1970
- Forced-Erasure Decoding and the Erasure Reconstruction Spectra for Group CodesIEEE Transactions on Communication Technology, 1967
- On decoding BCH codesIEEE Transactions on Information Theory, 1965