Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement
- 1 May 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (5) , 512-516
- https://doi.org/10.1109/t-c.1975.224254
Abstract
When errors occur which exceed the correction capability of an error correcting code, the only recourse to restore the original memory function is to physically replace the failed entity. In this paper the authors propose an automatic reconfiguration technique which uses the concept of address skewing to disperse such multiple errors into correctable errors. No additional redundancy other than that required for the error correcting code is needed. The skewing mechanism is derived using the theory of orthogonal Latin squares.Keywords
This publication has 3 references indexed in Scilit:
- Memories are bigger, fasterߝand cheaperIEEE Spectrum, 1973
- An 8-k bit random-access memory chip using a one-device FET cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- Orthogonal Latin Square CodesIBM Journal of Research and Development, 1970