A 1-Mbit Full-Wafer MOS RAM
- 1 August 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (4) , 677-686
- https://doi.org/10.1109/JSSC.1980.1051455
Abstract
A 3-in-diameter MOS RAM wafer with 1.256-Mbit net capacity has been designed. It is organized as two independent 32K word X 20 bit memories. Each 32K word memory comprises forty-six 20-kbit storage units, which, whether defective or not, are permanently connected to both buses and the power supply. Bit substitution and 32-word block substitution are used to counteract defects in storage units, and each wafer uses a combination of counter-measures against defects in its peripheral part. Fabricated RAM wafers showed 400-ns typical access time and 4.7-W power consumption at a 600-ns cycle time.Keywords
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