Programmable Connections in Neuromorphic Grids

1 August 2006

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1 (15483746) , 80-84
https://doi.org/10.1109/mwscas.2006.382000

Abstract

We describe asynchronous circuits that can relay spikes between multiple chips in a grid. These circuits interface with an on-chip SRAM to implement programmable connectivity among chips. We introduce a packet format that is compatible with updating the SRAM. From a high level specification, we synthesized and fabricated these circuits in an area of 0.206mm ² in 0.18- μ m CMOS technology. Test results that measure performance and demonstrate correct function on first silicon are presented.

Keywords

This publication has 9 references indexed in Scilit:

Neuromorphic implementation of orientation hypercolumns
IEEE Transactions on Circuits and Systems I: Regular Papers, 2005
Recurrently connected silicon neurons with active dendrites for one-shot learning
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
NEURONAL CIRCUITS OF THE NEOCORTEX
Annual Review of Neuroscience, 2004
A Burst-Mode Word-Serial Address-Event Link—I: Transmitter Design
IEEE Transactions on Circuits and Systems I: Regular Papers, 2004
A Multiconductance Silicon Neuron With Biologically Matched Dynamics
IEEE Transactions on Biomedical Engineering, 2004
512-Mb PROM with a three-dimensional array of diode/antifuse memory cells
IEEE Journal of Solid-State Circuits, 2003
A neuromorphic impulsive circuit for processing dynamic signals
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
Point-to-point connectivity between neuromorphic chips using address events
IEEE Transactions on Circuits and Systems II: Express Briefs, 2000
An Analog VLSI System for Stereoscopic Vision
Published by Springer Nature ,1994