A Burst-Mode Word-Serial Address-Event Link—I: Transmitter Design
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- 12 July 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 51 (7) , 1269-1280
- https://doi.org/10.1109/tcsi.2004.830703
Abstract
We present a transmitter for a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS. Transmission is initiated by active cells but cells are not read individually. An entire row is read in parallel; this increases communication capacity with integration density. Access is random but not inequitable. A row is not reread until all those waiting are serviced; this increases parallelism as more of its cells become active in the mean time. Row and column addresses identify active cells but they are not transmitted simultaneously. The row address is followed sequentially by a column address for each active cell; this cuts pad count in half without sacrificing capacity. We synthesized an asynchronous implementation by performing a series of program decompositions, starting from a high-level description. Links using this design have been implemented successfully in three generations of submicrometer CMOS technology.Keywords
This publication has 21 references indexed in Scilit:
- Communicating Neuronal Ensembles between Neuromorphic ChipsPublished by Springer Nature ,2007
- A Burst-Mode Word-Serial Address-Event Link—II: Receiver DesignIEEE Transactions on Circuits and Systems I: Regular Papers, 2004
- A Burst-Mode Word-Serial Address-Event Link—I: Transmitter DesignIEEE Transactions on Circuits and Systems I: Regular Papers, 2004
- A Burst-Mode Word-Serial Address-Event Link—III: Analysis and Test ResultsIEEE Transactions on Circuits and Systems I: Regular Papers, 2004
- A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversionIEEE Journal of Solid-State Circuits, 2001
- Point-to-point connectivity between neuromorphic chips using address eventsIEEE Transactions on Circuits and Systems II: Express Briefs, 2000
- A communication scheme for analog VLSI perceptive systemsIEEE Journal of Solid-State Circuits, 1995
- Artificial Dendritic TreesNeural Computation, 1993
- Silicon auditory processors as computer peripheralsIEEE Transactions on Neural Networks, 1993
- Scanners for visualizing activity of analog VLSI circuitryAnalog Integrated Circuits and Signal Processing, 1991