A 1-mil2single-transistor memory cell in N-silicon-gate technology
- 1 January 1973
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XVI, 30-31
- https://doi.org/10.1109/isscc.1973.1155226
Abstract
A cell design using a 4-μm width diffused bit line and a 5μm width aluminum word line contacted to a silicon gate over the channel region of the selection transistor of the memory cell will be described. Design of a sense-refresh circuit which can be used for 256 of the cells per amp will also be covered.Keywords
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- Storage array and sense/refresh circuit for single-transistor memory cellsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1972