LDMOS transistor for SMART POWER circuits: modeling and design
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper presents a compact model for circuit simulation. Physical properties and layout of the lateral MOSFET structure are considered. The model features a simple but accurate formulation of the drift resistance and the interelectrode capacitances. Experimental data characteristics are compared with simulated ones and very good agreement is found.Keywords
This publication has 4 references indexed in Scilit:
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