A divided/shared bitline sensing scheme for 64 Mb DRAM core
- 1 January 1990
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyondKeywords
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