A 4Mb DRAM with cross point trench transistor cell

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 268-269
https://doi.org/10.1109/isscc.1986.1156951

Abstract

This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.

Keywords

RANDOM ACCESS MEMORY
DECODING
CMOS TECHNOLOGY
DEAFNESS
DRIVER CIRCUITS
INSTRUMENTS
VEHICLES
LOG PERIODIC ANTENNAS
CMOS PROCESS
PLUGS

This publication has 3 references indexed in Scilit:

A 1Mb CMOS DRAM with design-for-test functions
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1986
A 1Mb CMOS DRAM with a divided bitline matrix architecture
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985
A trench transistor cross-point DRAM cell
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985