An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3

1 January 1981

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 812-819
https://doi.org/10.1109/dac.1981.1585450

Abstract

Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.

Keywords

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