Rapid yield estimation as a computer aid for analog circuit design
- 1 March 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (3) , 291-299
- https://doi.org/10.1109/4.75008
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Computer-aided design for VLSI circuit manufacturabilityProceedings of the IEEE, 1990
- OASYS: a framework for analog circuit synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- ISAAC: a symbolic simulator for analog integrated circuitsIEEE Journal of Solid-State Circuits, 1989
- IDAC: an interactive design tool for analog CMOS circuitsIEEE Journal of Solid-State Circuits, 1987
- BSIM: Berkeley short-channel IGFET model for MOS transistorsIEEE Journal of Solid-State Circuits, 1987
- A prototype framework for knowledge-based analog circuit synthesisPublished by Association for Computing Machinery (ACM) ,1987
- VLSI Yield Prediction and Estimation: A Unified FrameworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Parameter Extraction for Statistical IC Process CharacterizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Random errors in MOS capacitorsIEEE Journal of Solid-State Circuits, 1982
- Statistical Simulation of the IC Manufacturing ProcessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982