Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper describes the design, development and implementation of the program SPECS. The purpose of SPECS is to automatically extract from a Rockwell microelectronic symbolic matrix description a netlist for circuit simulation. This program differs from others in that it uses a symbol layout matrix as an input, calculates both interelectrode and intrinsic capacitance, calculates conductor resistance, produces a schematic representation of the network and has a selective TRACE, i.e., traces only the circuit or network of interest.Keywords
This publication has 8 references indexed in Scilit:
- VLSI parasitic capacitance determination by flux tubesIEEE Circuits & Systems Magazine, 1982
- Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI ChipsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Synchronous path analysis in MOS circuit simulatorPublished by Association for Computing Machinery (ACM) ,1982
- Coupling capacitances for two-dimensional wiresIEEE Electron Device Letters, 1981
- MULGA-An Interactive Symbolic Layout System for the Design of Integrated CircuitsBell System Technical Journal, 1981
- Circuit Simulation and Timing Verification based on MOS/LSI Mask InformationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Topological Analysis for VLSI CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Resistance calculations for thin film patternsThin Solid Films, 1968