Circuit Simulation and Timing Verification based on MOS/LSI Mask Information
- 1 January 1979
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A mask analysis program for MOS/LSI mask layout data has been developed. This program converts all the mask layout data in one chip LSI into the corresponding circuit schema. A partitioning method for the large random logic circuit divides it into small subcircuits. It is shown that this method takes full advantage of the savings both in computer time and computer storage for the circuit simulation and timing verification of the random logic circuit having more than 500 active devices.Keywords
This publication has 6 references indexed in Scilit:
- Choosing the right programs for computer-aided design: Electron. (29 April 1976), pp 102–105Computer-Aided Design, 1977
- A latent macromodular approach to large-scale sparse networksIEEE Transactions on Circuits and Systems, 1976
- MOTIS-An MOS timing simulatorIEEE Transactions on Circuits and Systems, 1975
- DC Model for short-channel IGFET'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- Device design considerations for ion implanted MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- Ion-implanted complementary MOS transistors in low-voltage circuitsIEEE Journal of Solid-State Circuits, 1972