A 15-ns 32*32-b CMOS multiplier with an improved parallel structure
- 1 April 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 25 (2) , 494-497
- https://doi.org/10.1109/4.52175
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- SPIM: a pipelined 64*64-bit iterative multiplierIEEE Journal of Solid-State Circuits, 1989
- A 45ns 16×16 CMOS multiplierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A high speed and low power CMOS/SOS multiplier-accumulatorMicroelectronics Journal, 1983
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- A SIGNED BINARY MULTIPLICATION TECHNIQUEThe Quarterly Journal of Mechanics and Applied Mathematics, 1951