Design of a BIST RAM with row/column pattern sensitive fault detection capability
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Row/column pattern sensitive fault detection in RAMs via built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 60-ns 4-Mbit CMOS DRAM with built-in selftest functionIEEE Journal of Solid-State Circuits, 1987
- Functional Testing of Semiconductor Random Access MemoriesACM Computing Surveys, 1983
- Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access MemoriesIEEE Transactions on Computers, 1980
- Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"IEEE Transactions on Computers, 1979
- Efficient Algorithms for Testing Semiconductor Random-Access MemoriesIEEE Transactions on Computers, 1978
- An Optimal Algorithm for Testing Stuck-at Faults in Random Access MemoriesIEEE Transactions on Computers, 1977
- Techniques for testing the microcomputer familyProceedings of the IEEE, 1976
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976
- Detection oF Pattern-Sensitive Faults in Random-Access MemoriesIEEE Transactions on Computers, 1975