A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 950-952
- https://doi.org/10.1109/iedm.1991.235269
Abstract
A novel 0.1- mu m-gate elevated source and drain MOSFET was fabricated utilizing phase-shifted lithography. Phase-shifted lithography enabled less than 0.2- mu m spacing, resulting in a 0.1- mu m gate length in combination with a side-wall oxide film formation technique. It is concluded that the new gate definition process utilizing phase-shifted lithography will be promising for future ultrasmall device fabrication.<>Keywords
This publication has 1 reference indexed in Scilit:
- Design and experimental technology for 0.1-µm gate-length low-temperature operation FET'sIEEE Electron Device Letters, 1987