Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's

1 October 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 8 (10) , 463-466
https://doi.org/10.1109/edl.1987.26695

Abstract

The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FET's.

Keywords

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