Generalized scaling theory and its application to a ¼ micrometer MOSFET design
- 1 April 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 31 (4) , 452-462
- https://doi.org/10.1109/t-ed.1984.21550
Abstract
In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved.Keywords
This publication has 36 references indexed in Scilit:
- Transconductance degradation in thin-Oxide MOSFET'sIEEE Transactions on Electron Devices, 1983
- Spreading resistance in submicron MOSFET'sIEEE Electron Device Letters, 1983
- Electrical Properties of Al/Ti Contact Metallurgy for VLSI ApplicationJournal of the Electrochemical Society, 1982
- Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror imagesIEEE Transactions on Electron Devices, 1982
- Use of process and 2-D MOS simulation in the study of doping profile influence on S/D resistance in short channel MOSFET'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Experimental and theoretical characterization of submicron MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- 1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applicationsIEEE Journal of Solid-State Circuits, 1979
- Properties of Semiconductor Surface Inversion Layers in the Electric Quantum LimitPhysical Review B, 1967
- Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistorsSolid-State Electronics, 1966