Integrated low noise, low power, fast charge-sensitive preamplifier for avalanche photodiodes in JFET-CMOS-technology
- 11 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 9/59-9/63 vol.2
- https://doi.org/10.1109/nssmic.2000.949871
Abstract
To take advantage on the compactness of APD arrays, low noise, power efficient, fast charge sensitive preamplifier chips with differential current drivers have been developed. A 16-channel and a single channel version are available. The chips were adapted for low capacitance 4/spl times/8 APD arrays produced by Hamamatsu, Japan. A mixed JFET-CMOS production process yielded high quality integrated JFETs for the input stage of the amplifier's folded cascode. Thus, the 1/f-noise corner is kept at 4 kHz. The JFET has a transconductance of 11 mS at a drain current of 3 mA. The serial noise of the input transistor was found to be 0.8 nV//spl radic/Hz. The signal rise-time of the driver outputs is 20 ns. The rms noise of the preamplifier was found to be 480 e/sup -/ with a 25 e/sup -//pF noise slope for a shaping time of 50 ns. The serial input noise of the preamplifier is about 1.7 nV//spl radic/Hz from 200 kHz up to 40 MHz and the 1/f-noise corner is at 70 kHz. The power consumption is 30 mW per preamplifier, including the differential driver. The linearity is better than 1.3% over 48 dB dynamic range. For the 16 channel chip, the gain variation is less than 3.5%. Performance similar to PMTs can be achieved with APDs in combination with this integrated preamplifier chip.Keywords
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