A fast 256K DRAM designed for a wide range of applications
- 1 October 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (5) , 602-609
- https://doi.org/10.1109/JSSC.1984.1052196
Abstract
A 256K DRAM designed for a variety of organizations and operation modes is described. The chip may be organized as 64K/spl times/4, 128K/spl times/2, or 256K/spl times/1. Four data I/O buffers are selectable by gate signals. Besides the standard RAM mode, it may be operated in the page mode, in the parallel or serial buffer mode, and in a combination of page and serial buffer modes. With these options, the design covers a wide range of applications. RAS/CAS access times are 80.55 ns. In the combined page and serial buffer mode, a data rate of up to 50 MHz is possible. The chip is built in metal-gate n-channel technology with 2-/spl mu/m minimum line width and two metal interconnection planes.Keywords
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