Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs
- 1 January 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1 (15301591) , 1-6
- https://doi.org/10.1109/date.2006.243994
Abstract
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (network-on-chip), targeted at future power-efficient systems. The proposed solution is based on the idea of locally performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e.g. spin locks). We introduce a HW module, the synchronization-operation buffer (SB), which queues and manages the requests issued by the processors. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For 8-processor target architecture, we show that the proposed solution achieves up to 40% performance improvement and 30% energy saving with respect to synchronization based on directory-based coherence protocolKeywords
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