A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D Converter
- 1 January 1995
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 276-277,
- https://doi.org/10.1109/isscc.1995.535554
Abstract
In bipolar technology the folding and interpolation technique has proven to be successful for high sample rates. This paper investigates the possibilities of this technique in CMOS. The major advantage of folding and interpolation in CMOS lies in the field of high sample rate in combination with low power consumption and small chip area. The folding converter requires little power to drive the input compared to other converters since the input behaves like a linear and constant capacitor. For similar reasons the power consumption of the reference ladder of the folding converter can be kept low. The circuit reported here runs at 70 MSample/s and dissipates only 110 mW. There are versions for 5 V and 3.3 V supplies and they are realized in a 0.8 μm CMOS processKeywords
This publication has 5 references indexed in Scilit:
- A CMOS 40 MHz 8 b 105 mW two-step ADCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 100 MHz 8 bit CMOS interpolating A/D converterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOSIEEE Journal of Solid-State Circuits, 1993
- An 8-b 650-MHz folding ADCIEEE Journal of Solid-State Circuits, 1992
- An 8-bit video ADC incorporating folding and interpolation techniquesIEEE Journal of Solid-State Circuits, 1987