A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
- 1 November 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (11) , 1770-1779
- https://doi.org/10.1109/jssc.1996.542322
Abstract
A 4 mm/sup 2/, two-dimensional (2-D) 8/spl times/8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-/spl mu/m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V/sub DD/-V/sub th/ design space is also studied.Keywords
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