LAYIN: toward a global solution for parasitic coupling modeling and visualization
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- AWE-InspiredPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Chip Substrate Resistance Modeling Technique for Integrated Circuit DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984