A comprehensive delay macro modeling for submicrometer CMOS logics
- 1 January 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (1) , 42-55
- https://doi.org/10.1109/4.736655
Abstract
No abstract availableThis publication has 20 references indexed in Scilit:
- Design and selection of buffers for minimum power-delay productPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A model for delay evaluation of a CMOS inverterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Delay modelling improvement for low voltage applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Methods to improve digital MOS macromodel accuracyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- Explicit evaluation of short circuit power dissipation for CMOS logic structuresPublished by Association for Computing Machinery (ACM) ,1995
- Digital Timing Macromodeling for VLSI Design VerificationPublished by Springer Nature ,1995
- Inverter models of CMOS gates for supply current and delay evaluationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Process characterisation with dynamic test structuresElectronics Letters, 1993
- Synchronous-mode evaluation of delays in CMOS structuresIEEE Journal of Solid-State Circuits, 1991
- Delay analysis of series-connected MOSFET circuitsIEEE Journal of Solid-State Circuits, 1991