Dispersion and tunneling analysis of the interfacial gate resistance in Schottky barriers

We present a theoretical explanation of the interfacial component in the gate resistance of Schottky-barrier-gate field-effect transistors (SBGFETs). This component was recently established and was found, for GaAs- and InP-based SBGFETs, to have the smallest practically achievable normalized value $r_{\mathrm{gi}}$ on the order of ${10}^{-7}\hspace{0.5em}\Omega {\mathrm{cm}}^2.$ We show that $r_{\mathrm{gi}}$ in this range can be modeled as an ac tunneling resistance $r_{\mathrm{IT}}$ between the three-dimensional (3D) gate metal and the 2D semiconductor surfaces states. We extend Cowley and Sze’s static Schottky-barrier lineup model to include high-frequency modulation of the surface-state occupation by an ac gate voltage. We find that, since $r_{\mathrm{IT}}$ is not simply a dc resistance in series with the standard parasitic gate resistance, the resulting experimentally observed $r_{\mathrm{gi}}$ is smaller by an amount that depends on the interfacial layer and surface-state density. However, for the typically observed values, $r_{\mathrm{gi}}$ acts like a series resistance up to presently attainable frequencies. Thus, while Cowley and Sze’s phenomenological “interfacial layer of the order of atomic dimensions” is more or less “transparent to electrons,” it presents a resistance that cannot be ignored at microwave and millimeter-wave frequencies. We apply our theory using interfacial-layer parameter values corresponding to alternative models for Schottky-barrier formation, and compare the predictions to experimental observations. Our results are consistent with models that involve defects near the semiconductor-metal interface.