Reconfiguration of VLSI/WSI mesh array processors with two-level redundancy
- 1 April 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 38 (4) , 547-554
- https://doi.org/10.1109/12.21147
Abstract
Reconfiguration schemes for replacing faulty cells (processing elements) with spare cells are introduced for massive parallel rectangular mesh array processors with fine-grained cells. The authors introduce the concept of two-level redundancy as an effective way of using redundant units to reduce the complexity of reconfiguration control circuitry, to limit the length of connecting wires after reconfiguration, and to increase the manufacturing yield and the operation reliability. An optimization technique for allocating the redundant cells into both levels is presented. The operational reliability and manufacturing yield of arrays with two-level redundancy are presented. The yield estimation problem is modeled by an occupancy problem in classical combinatorial analysis. Both distributed and clustered defects are taken into consideration in the yield estimation.Keywords
This publication has 8 references indexed in Scilit:
- Modeling the Effect of Redundancy on Yield and Performance of VLSI SystemsIEEE Transactions on Computers, 1987
- Efficient Spare Allocation for Reconfigurable ArraysIEEE Design & Test of Computers, 1987
- Reconfigurable architectures for VLSI processing arraysProceedings of the IEEE, 1986
- Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI DesignsIEEE Transactions on Computers, 1982
- Why systolic architectures?Computer, 1982
- Design of a Massively Parallel ProcessorIEEE Transactions on Computers, 1980
- Defect density distribution for LSI yield calculationsIEEE Transactions on Electron Devices, 1973
- Cost-size optima of monolithic integrated circuitsProceedings of the IEEE, 1964