Automatic synthesis and verification of hazard-free control circuits from asynchronous finite state machine specifications
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
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This publication has 2 references indexed in Scilit:
- Synthesis of hazard-free asynchronous circuits from graphical specificationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Automatic synthesis of locally-clocked asynchronous state machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002