Automatic synthesis of locally-clocked asynchronous state machines
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors describe a novel automated design methodology for asynchronous state-machine controllers. Using a local-clocking scheme, the method allows multiple input changes and produces hazard-free designs with a minimal or near-minimal number of states. The authors present an automated program for asynchronous state machine synthesis, and describe a new heuristic for state minimization and new optimizations to improve implementations. The program is used to synthesize competitive implementations of published designs; results are compared.Keywords
This publication has 11 references indexed in Scilit:
- Translating concurrent programs into delay-insensitive circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis of asynchronous state machines using a local clockPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Specification, Synthesis, and Verification of Hazard-Free Asynchronous CircuitsPublished by Springer Nature ,1994
- Synthesis of multiple-input change asynchronous finite state machinesPublished by Association for Computing Machinery (ACM) ,1991
- Algorithms for synthesis of hazard-free asynchronous circuitsPublished by Association for Computing Machinery (ACM) ,1991
- MicropipelinesCommunications of the ACM, 1989
- Direct Implementation of Asynchronous Control UnitsIEEE Transactions on Computers, 1982
- Stored State Asynchronous Sequential CircuitsIEEE Transactions on Computers, 1981
- Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-FlopsIEEE Transactions on Computers, 1973
- Internal State Assignments for Asynchronous Sequential MachinesIEEE Transactions on Electronic Computers, 1966