Some Performance Issues in Multiprocessor System Design

1 May 1977

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-26 (5) , 506-511
https://doi.org/10.1109/tc.1977.1674868

Abstract

Analytic and simulation models of memory interference have been reported in the literature. These models provide tools for analyzing various system architecture alternatives. Some of the design parameters are processor speed, memory speed, number of processors, number of memories, use of cache memories, high-order versus low-order interleaving, and memory allocation. This correspondence applies existing analytic and simulation models to the multiprocessor design space and presents guidelines for the multiprocessor system architect. Preferred design alternatives and tradeoffs are outlined.

Keywords

This publication has 5 references indexed in Scilit:

Cache memories for PDP-11 family computers
Published by Association for Computing Machinery (ACM) ,1976
On the Performance of Certain Multiprocessor Computer Organizations
IEEE Transactions on Computers, 1975
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers, 1975
HYDRA
Communications of the ACM, 1974
Communication processors
Proceedings of the IEEE, 1972