Efficient analysis of buffered multistage switching networks under bursty traffic
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1072-1078 vol.2
- https://doi.org/10.1109/glocom.1993.318241
Abstract
Many large-scale switching networks for B-ISDN will be built using several stages of smaller switching elements. Previous analyses of these multistage networks have mainly focused on memoryless arrival processes. In this paper, we present an efficient method for analyzing the performance of buffered switching networks using cut-through routing and back-pressure mechanism under bursty traffic conditions. The traffic flows are modeled using stochastic fluid processes. Unlike previous related work, the analysis is independent of the size of the buffers and polynomial in the number of sources feeding the buffer. Performance measures including delay and loss probabilities are derived. The analysis also yields information on loss periods at the first stage and on traffic burstiness throughout the switch. Our analytic results, which are validated by simulation, suggest that traditional analyses of buffered switching networks assuming memoryless arrival processes may incur large errors when the input traffic is actually bursty. Our analysis extends naturally to various switching architectures.Keywords
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