Exploiting instruction-level resource parallelism for transparent, integrated control-flow monitoring
- 10 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 318-325
- https://doi.org/10.1109/ftcs.1991.146680
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- A study of time-redundant fault tolerance techniques for high-performance pipelined computersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Continuous signature monitoring: efficient concurrent-detection of processor control errorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Saturation: reduced idleness for improved fault-tolerancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A superpipeline approach to the MIPS architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The nonuniform distribution of instruction-level and machine parallelism and its effect on performanceIEEE Transactions on Computers, 1989
- A VLIW architecture for a trace scheduling compilerACM SIGARCH Computer Architecture News, 1987
- Processor Control Flow Monitoring Using Signatured Instruction StreamsIEEE Transactions on Computers, 1987
- Very Long Instruction Word architectures and the ELI-512Published by Association for Computing Machinery (ACM) ,1983
- Concurrent Error Detection in ALU's by Recomputing with Shifted OperandsIEEE Transactions on Computers, 1982
- FTMP—A highly reliable fault-tolerant multiprocess for aircraftProceedings of the IEEE, 1978