Scaling tradeoffs for CMOS-based VLSI packaging

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 621-633
https://doi.org/10.1109/ectc.1995.515348

Abstract

Scaling tradeoffs for terminations and interconnects with pre-specified overall system performance are discussed in this paper. If the overall performance requirements are to be met, it is shown that to scale the interconnect cross section with a specified scaling factor S c 2 requires a scaling factor less than S c for driver area and receiver area. Closed-form expressions for the required effective driver resistance and for the required effective load capacitance are given. For cases with fixed dimensionless driver resistance, several possible scaling scenarios for interconnects with different scaling factors are discussed. It is found that to avoid performance degradation the line spacing should be scaled by a smaller factor than that for other package dimensions. In other words, scaling with a fixed dimensionless driver resistance requires decreased line coupling. Scaling for package cross-sections (including line spacing) with fixed driver resistance also is investigated by scaling dielectric constant. It is shown that a smaller dielectric constant for the scaled package than that for unsealed structure is needed to meet the overall performance requirements. For cases with increased line length, scaling for package cross-sections becomes limited. Our studies also show strong dependence of the scaling tradeoffs on the choice of packaging structure that is to be scaled Author(s) Yaochao Yang Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA Brews, J.R.

Keywords

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