A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture
- 1 April 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (4) , 487-493
- https://doi.org/10.1109/4.499724
Abstract
No abstract availableKeywords
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