Design of PLL-based clock generation circuits
- 1 April 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (2) , 255-261
- https://doi.org/10.1109/jssc.1987.1052710
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- A novel precision MOS synchronous delay lineIEEE Journal of Solid-State Circuits, 1985
- The Modular Design of Clock-Generator Circuits in a CMOS Building-Block SystemIEEE Journal of Solid-State Circuits, 1985
- Phase Accuracy of Charge Pump PLL'sIEEE Transactions on Communications, 1982
- A synchronous approach for clocking VLSI systemsIEEE Journal of Solid-State Circuits, 1982
- Low power PCM CODEC and filter systemIEEE Journal of Solid-State Circuits, 1981
- Charge-Pump Phase-Lock LoopsIEEE Transactions on Communications, 1980