A synchronous approach for clocking VLSI systems
- 1 February 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (1) , 51-56
- https://doi.org/10.1109/jssc.1982.1051685
Abstract
Presents a synchronous solution for clocking VLSI systems organized as distributed systems. This solution avoids the drawbacks of the self-timed approach. These VLSI systems are constituted of modules which represent synchronous areas driven by their own fast clock, interconnected by a synchronous communication mechanism driven by a slow clock. In order to avoid the risk of metastability in flip-flop between the modules and the communication mechanism, the author suggests to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.Keywords
This publication has 4 references indexed in Scilit:
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