The Weighted Random Test-Pattern Generator
- 1 July 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (7) , 695-700
- https://doi.org/10.1109/t-c.1975.224290
Abstract
A heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuits. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault-detecting patterns.Keywords
This publication has 2 references indexed in Scilit:
- Algorithms for Detection of Faults in Logic CircuitsIEEE Transactions on Computers, 1971
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966