Multiple-valued Boolean minimization based on graph coloring

Publisher Website

7 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iccd.1989.63367

Abstract

No abstract available

Keywords

This publication has 6 references indexed in Scilit:

Multiple-Valued Minimization for PLA Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
PALMINI---fast Boolean minimizer for personal computers
Published by Association for Computing Machinery (ACM) ,1987
Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
Input Variable Assignment and Output Phase Optimization of PLA's
IEEE Transactions on Computers, 1984
Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays
IEEE Transactions on Computers, 1981
MINI: A Heuristic Approach for Logic Minimization
IBM Journal of Research and Development, 1974